As memory sizes increase, the range of applications using non-volatile memories increases sharply. For example, it has already become possible to store audio in non-volatile solid-state memories, e.g. using MP3 coding. It is expected that in the foreseeable future it will be possible to store a movie in a non-volatile memory at reasonable costs. Using such non-volatile memories enables relatively cheap and reliable rendering devices, such as an MP3 player, and opens many new applications in hand-held computer-like devices, such as PDAs and new generation mobile phones. Magnetic or Magnetoresistive Random Access Memory (MRAM) is currently being considered by many companies as a successor to flash memory. It has the potential to replace all but the fastest static RAM (SRAM) memories. It is a non-volatile memory device, which means that no power is required to sustain the stored information. This is seen as an advantage over most other types of solid-state memory. The MRAM concept uses magnetisation direction in a magnetic multilayer device as information storage and the resultant resistance difference for information readout. Each magnetic memory cell is able to store at least two states which represent either a “1” or a “0”. An array of magnetic memory cells is often called magnetic RAM or MRAM.
Different kinds of magnetoresistive (MR) effects exist, such as the anisotropic magnetoresistive (AMR) effect and the Giant Magneto-Resistance effect (GMR). For MRAMs, it is preferred that the Tunnel Magneto-Resistance (TMR) effect is used. In a Magnetic Tunnel Junction (MTJ), the memory cells are formed using a stack of thin films of which at least two are ferromagnetic or ferrimagnetic, and which are separated by an insulating tunnel barrier. The magnetoresistance results from the spin-polarized tunnelling of conduction electrons between the two ferromagnetic or ferrimagnetic layers. The tunnelling current which flows in the perpendicular direction to the plane of the stack depends on the relative orientation of the magnetic moments of the two ferromagnetic or ferrimagnetic layers. The tunnelling current is observed to be the largest (or thus resistance to be the smallest) when the magnetisation directions of the films are parallel and tunnelling current is the smallest (or thus resistance the largest) when the magnetisation directions of the films are anti-parallel.
MTJ memory elements generally include a layered structure comprising a fixed or pinned ferromagnetic layer (PFL), a free ferromagnetic layer (FFL) and a dielectric barrier in between. The PFL layer has a magnetic vector that always points in the same direction. The magnetic vector of the FFL layer is free, but constrained within the easy axis of the layer, which is determined chiefly by the physical dimensions of the element. The magnetic vector of the free layer points in either of two directions: parallel or anti-parallel with the magnetisation direction of the pinned layer, which coincides with the said easy axis. These two possible directions of magnetization of the FFL layer along this easy axis define the two states of the memory cell. The magnetization direction of the PFL layer is more difficult to change than that of FFL. In the range of fields applied by currents through the bit and word lines, the magnetization direction of PFL is fixed or pinned. The magnetic fields applied to write the memory cell are large enough to reverse the direction of magnetization of FFL, but not the direction of PFL. Thus, the magnetization of PFL does not change direction during operation of the memory cells in the MRAM.
For accessing the memory elements, word lines and bit lines are patterned separately into two metal layers under and above the MTJ stack. Each memory element is located at a cross-point region of a word line and a bit line. Word lines extend along rows of memory elements, and bit lines extend along columns of memory elements. During reading a current is directed through a cell to be read. Since cells share word and bit lines, it is known to use for each cell a transistor to control through which cell the read current is fed. Such MRAMs are referred to as 1T1MTJ MRAMs (one-transistor per one MTJ cell). U.S. Pat. No. 5,640,343 describes an alternative MRAM that uses a diode per cell to control the reading. The advantage of this so-called 0T1MTJ MRAM is that it uses a small chip area FIG. 1 illustrates the known 0T1MTJ MRAM. The MRAM array of magnetoresistive memory cells includes a set of electrically conductive traces that function as parallel word lines WL1, WL2, and WL3, and in a horizontal plane, and a set of electrically conductive traces that function as parallel bit lines BL1, BL2, and BL3 in another horizontal plane. The bit lines are oriented in a different direction, usually at right angles to the word lines, so that the two sets of lines intersect when viewed from above. A memory cell, such as typical memory cell 10, is located at each crossing point of the word lines and bit lines in the intersection region vertically spaced between the lines. The memory cell 10 is arranged in a vertical stack and may include a diode-like device 7 and a magnetic tunnel junction (MTJ) 8. During operation of the array, current flows in a vertical direction through the cell 10. The vertical current path through the memory cell permits the memory cell to occupy a very small surface area. Contact to the word lines, the MTJ, the diode, and the contact to the bit line all occupy the same area. The array is formed on a substrate, such as a silicon substrate on which there would be other circuitry (not shown). The detailed construction of the diode-like device and the MTJ are not relevant for the invention.
The MTJ 8 changes resistance when the direction of magnetization of the FFL switches from being parallel to being antiparallel to the magnetization direction of PFL. As will be explained, this occurs as a result of magnetic fields generated when current is passed through the bit and word lines. When a sufficiently large current is passed through both a write line and a bit line of the MRAM, the self-field of the so combined currents at the intersection of the write and bit lines will rotate the magnetization of the FFL of the single particular MTJ located at the intersection of the energized write and bit lines. The current levels are designed so that the combined self-field exceeds the switching field of the FFL. This self-field is designed to be much smaller than the field required to rotate the magnetization of the PFL. The cell array architecture is designed so that the write currents do not pass through the MTJ itself. The memory cell is read by passing a sense current perpendicularly through the diode and MTJ from the PFL through the tunnel junction barrier to the FFL (or vice versa). The state of the memory cell is determined by measuring the resistance of the memory cell when a sense current, much smaller than the write currents, is passed perpendicularly through the MTJ. The self-field of this sense or read current is negligible and does not affect the magnetic state of the memory cell. The tunneling current is spin polarized, which means that the electrical current passing from one of the ferromagnetic layers, for example, the PFL, is predominantly composed of electrons of one spin type (spin up or spin down, depending on the orientation of the magnetization of the ferromagnetic layer). The tunneling probability of the charge carriers is highest when the magnetic moments of both layers are parallel, and is lowest when the magnetic moments are antiparallel. As a result, the two possible magnetization directions of the FFL uniquely define two possible bit states (0 or 1) of the memory cell.
To read and write the 0T1MTJ MRAM only the bit lines and the word lines are required; no other control lines from outside the array are necessary to read or write the memory state of the memory cells. This provides a very efficient memory array. A selected cell, e.g. cell 10 of FIG. 1, is written by passing current Ib through the bit line BL3 and current Iw through word line WL3 connected to the cell 10. Bit line control circuitry is attached to the bit lines and controls Ib. Word line control circuitry is attached to the word lines and controls Iw. The magnetic field produced by either Ib or Iw alone in the region of the cells is less than the magnetic field required to change the magnetic state in a cell, so half-selected cells (those over which only Ib or Iw alone is passing) are not written. However, the combination of magnetic fields from Ib and Iw is sufficient to change the state of selected memory cell 10. At least one of the currents Ib or Iw has to be reversible to write the two different magnetic states of the cell 10. The bit lines are also connected to the sensing circuitry, which may be part of bit line control circuitry. The voltage level of the bit lines during a write operation is near a voltage Vb for convenience in providing for the bidirectional currents. The voltage level of the word lines is near a more positive voltage Vw. The voltage levels are selected to ensure that all diodes in the array are reverse biased so that the currents Ib and Iw do not flow vertically through any memory cell. In a read operation a forward bias voltage is established across the selected cell 10 by pulling the word line WL3 voltage down to Vb, and raising the bit line BL3 voltage to Vw. During a read, unselected bit lines BL1, BL2 remain at the standby voltage level Vb, and unselected word lines WL1, WL2 remain at the standby voltage level Vw. Half-selected cells have zero voltage drop from word line to bit line and do not conduct. The resistance of the selected memory cell determines the sense current that flows from the bit line through the selected memory cell to the word line. In the sense circuitry, this current is compared to a reference current set to a value halfway between the expected values for the two possible states of the memory cell and the difference is amplified to read the data stored in selected cell 10.
In particular for mobile devices, it is very important to reduce the power consumption of memory devices. For non-volatile memories in general the writing operation is most power-consuming. For example, a write operation on MRAM elements involves two current pulses of several mA, that must be sent simultaneously through a bit line and a word line for each bit of a word to be written.